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Semiconductor
NOT
October 1998
R D FO NDE I3086 E OMM See H REC
D NEW
ESIG
NS
HI1826
6-Bit, 140 MSPS, Flash A/D Converter
Description
HI1826 is a 6-bit, 140 MSPS, flash A/D converter IC capable of digitizing analog signals at the maximum rate of 140 MSPS. The digital input/output level is compatible with the ECL 100K/10KH/10K.
Features
* Ultra-High Speed Operation with Maximum Conversion Rate. . . . . . . . . . . . . . . . . . . . . . . 140 MSPS
[ /Title (HI1826) * Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . 7pF /Subject (6-Bit, 140 MSPS, Flash A/D Converter) * Wide Analog Input Bandwidth (Min) . . . . . . . . 200MHz /Author () /Keywords Consumption . . . . . . . . . . RGB, Video, FlatOrdering Information * Low Power(Harris Semiconductor, . . . . . . . .225mW Panel,Error Rate PART TEMP. * Low LCD) NUMBER RANGE (oC) /Creator () /DOCINFO pdfmark Applications HI1826JCQ -20 to 75
* RGB Graphics Processing
PACKAGE 32 Ld MQFP
PKG. NO. Q32.7x7-S
[ /PageMode /UseOutlines * Digital Data Storage Read Channels /DOCVIEW pdfmark
* Digital Communications
Pinout
HI1826 (MQFP) TOP VIEW
D0 (LSB)
DGND1 DGND2 NC NC NC NC DGND2 DGND1
1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16
AGND
CLKN
CLKP
DVEE
AVEE
D2
D1
VRTS VRT AGND NC VIN AGND VRB VRBS
D3
D4
D5 (MSB)
AGND
DVEE
AVEE
INV
NC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
(c) Harris Corporation 1998
File Number
4107.2
4-1
HI1826 Block Diagram
VRB 18 VRBS 17 VRTS 24 VRT 23
REFERENCE RESISTANCE 20 VIN
COMPARATOR ARRAY 8 7 ENCODER LOGIC DGND1 DGND2
19 AGND 12 DVEE
6 15 AVEE INV 13 EXOR ARRAY 6 CLKP 28 CLK DRIVER CLKN 27 OUTPUT BUFFER
30
31
32 D2
9 D3
10 D4
11 D5 (MSB)
D0 D1 (LSB)
4-2
HI1826 Pin Descriptions
TYPICAL VOLTAGE LEVEL 0V
PIN NO. 16, 19, 22, 25
SYMBOL AGND
I/O -
EQUIVALENT CIRCUIT
DESCRIPTION Analog GND. Used as GND for input buffers and latches of comparators. Separated from DGND1 and DGND2. Analog VEE . Typical voltage is -5.2V. Connected internally with DVEE . (Resistance is 4 to 6.) Connect to AGND through a ceramic chip capacitor of 0.1F or more just near the pin.
15, 26
AVEE
-
-5.2V
28 27
CLKP CLKN
I
ECL
DGND1
CLK Input. CLK Complementary Input. When left open, voltage goes to ECL threshold potential (-1.3V). Although only CLKP input can be used for operation with CLKN input open, complementary input is recommended in order to attain high speed and stable operation.
R R CLKP R
R
CLKN
R DVEE
R
1, 8 2, 7 12, 29
DGND1 DGND2 DVEE
-
0V 0V -5.2V
Digital GND for Internal Circuits. Digital GND for Output Transistors. Digital VEE. Connected internally with AVEE. (Resistance is 4 to 6.) Connect to DGND through a ceramic chip capacitor of 0.1F or more just near the pin.
DGND2
30
D0
O
ECL
LSB of Data Output. External pull-down resistor is required. Data Output. External pull-down resistors are required.
31 32 9 10 11
D1 D2
Di
D3 D4 D5 MSB of Data Output. External pull-down resistor is required.
DVEE
4-3
HI1826 Pin Descriptions
(Continued) TYPICAL VOLTAGE LEVEL ECL
DGND1
PIN NO. 13
SYMBOL INV
I/O I
EQUIVALENT CIRCUIT
DESCRIPTION Output polarity inversion input for D0 (LSB) to D5 (MSB). (Refer to the output code table.) When left open, Low levels maintained.
R R INV R -1.3V
DVEE
R
20
VIN
I
VRT to VRB
AGND VIN
Analog Input.
AVEE
18
VRB
I
-2V
VRT
R1 R COMPARATOR 1 R COMPARATOR 2
VRTS
Reference Voltage (Bottom) Force; typical voltage is -2V. Connect to AGND through a ceramic chip capacitor of 0.1F or more and a tantalum capacitor of 10F or more just near the pin. Reference Voltage (Bottom) Sense. Reference Voltage (Top) Force; typical voltage is 0V. When applying a voltage other than AGND to this pin, connect to AGND through a ceramic chip capacitor of 0.1F for more and a tantalum capacitor of 10F or more just near the pin. Reference Voltage (Top) Sense.
17 23
VRBS VRT I 0V
R COMPARATOR 30 R COMPARATOR 31
24
VRTS
R COMPARATOR 32 R COMPARATOR 33
R COMPARATOR 63 VRBS VRB R3 R
3, 4 5, 6 14, 21
NC
-
-
Not Connected. Although not connected in the IC, it is recommended that these pins should be connected to AGND or DGND on printed circuit board.
4-4
HI1826
Absolute Maximum Ratings
TA = 25oC
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (Lead Tips Only)
Supply Voltage (AVEE) . . . . . . . . . . . . . . . . . . . . . . . . . . -7V to 0.5V Reference Voltage (VRT , VRB) . . . . . . . . . . . . . . . . . . . -1.5V to 0.5V | VRT - VRB | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V Analog Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . -2.7V to 0.5V Digital Input Voltage (CLKP, CLKN, INV) . . . . . . . . . . . . -4V to 0.5V | CLKP - CLKN | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V Digital Output Current (ID0 to ID5) . . . . . . . . . . . . . . . -30mA to 0mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . -20oC to 75oC Supply Voltage AVEE , DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5V to -4.95V AVEE , DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V AGND, DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V Reference Voltage VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.1V to 0.1V VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.2V to -1.8V Analog Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . VRB to VRT Clock Pulse Width tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0ns tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0ns
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Resolution DC CHARACTERISTICS Integral Linearity Error Differential Linearity Error ANALOG INPUT Analog Input Capacitance Analog Input Resistance Input Bias Current REFERENCE INPUT Reference Resistance Offset Voltage VRT VRB DIGITAL INPUT Logic High Level Logic Low Level Logic High Current Logic Low Current Input Capacitance
VDD = +5V, VRB = 1.0V, VRT = 2.0V, TA = 25oC SYMBOL n TEST CONDITIONS MIN 6 TYP 6 MAX 6 UNITS bits
EIL EDL
fC = 140MHz fC = 140MHz
-0.25 -0.25
-
+0.25 +0.25
LSB LSB
CIN RIN IIN
VIN = -1V + 0.07VRMS
300
7 -
18 400
pF k A
VIN = -1V
-
RREF EOT EOB
-
200 -
20 20
mV mV
VIH VIL IIH IIL Apply -0.8V to Input Apply -1.6V to Input
-1.13 -2.1 0 -50 -
7
-0.65 -1.5 50 50
V V A A pF
SWITCHING CHARACTERISTICS Maximum Conversion Frequency Aperture Jitter fC tAJ Error rate 1E-9 TPS (Note 1) 140 10 MSPS ps
4-5
HI1826
Electrical Specifications
PARAMETER Sampling Delay High Pulse Width of Clock Low Pulse Width of Clock DIGITAL OUTPUT Logic High Level Logic Low Level Output Delay Output Rise Time Output Fall Time DYNAMIC CHARACTERISTICS Analog Input Bandwidth Error Rate S/N Ratio SNR fCLK = 140MHz, fIN = 69.999MHz Error Amplitude 4 LSB -3dB fS fCLK = 140MHz, fIN = 1MHz fCLK = 140MHz, fIN = 35MHz POWER SUPPLY Supply Current Power Consumption Note 1. TPS: Times Per Sample IEE PD AVEE = DVEE = -5.2V -60 -40 225 -25 mA mW 200 36 34 1E-09 MHz TPS (Note 1) dB dB VOH VOL tDO tr tf RL = 100 to -2V RL = 100 to -2V RL = 100 to -2V RL = 100 to -2V, 20% to 80% RL = 100 to -2V, 20% to 80% -1.10 -2.1 3.0 3.6 0.8 1.0 -0.65 -1.6 4.2 V V ns ns ns VDD = +5V, VRB = 1.0V, VRT = 2.0V, TA = 25oC (Continued) SYMBOL tDS tPW1 tPW0 TEST CONDITIONS MIN 3.0 3.0 TYP 1.5 MAX UNITS ns ns ns
Output Code Table
INV: 1 VIN (NOTE) 0V STEP 0 1 D5 D0 INV:0 D5 D0
000000 000001
111111 111110
* * *
-1.0V 31 32 011111 100000
* * *
100000 011111
* * *
62 -2.0V 63 111110 111111
* * *
000001 000000
NOTE: VRT = 0V, VRB = -2V
4-6
HI1826 Timing Diagram
ANALOG IN N N+2 tPW1 CLKN CLKP tPW0 tDS N+1
DIGITAL OUT tDO
N-1 20%
80%
N
20%
N+1 80% tf
tr
Test Circuits
SIGNAL SOURCE fCLK 4 VIN HI1826 6 ECL LATCH A B ECL LATCH COMPARATOR A>B PULSE COUNTER
- 1kHz
CLKP
CLKN
+
2VP-P SINE WAVE DATA 4 SIGNAL SOURCE fCLK
1/
4
FIGURE 1. MAXIMUM CONVERSION RATE MEASUREMENT CIRCUIT
+V
S2
+
-
S1
S1: ON FOR AB 70MHz
VAB COMPARATOR VIN DUT HI1826 6 A6 A1 A0 DVM CLK (140MHz) CONTROLLER "0" B6 B1 B0 "1" 6 000000 TO 111110 OSC2 6 BUFFER fr
AMP
:VARIABLE
VIN HI1826 CLK 6 LOGIC ANALYZER 1024 SAMPLES ECL BUFFER 70MHZ
OSC1
FIGURE 2. INTEGRAL LINEARITY ERROR MEASUREMENT CIRCUIT, DIFFERENTIAL LINEARITY ERROR MEASUREMENT CIRCUIT
FIGURE 3. SAMPLING DELAY MEASUREMENT CIRCUIT APERTURE JITTER MEASUREMENT CIRCUIT
4-7
HI1826
IIN -1V A -2V
24 VRTS
23 VRT
22 AGND
21
20 VIN
19 AGND
18 VRB
17 VRBS AGND 16 AVEE 15 14 INV 13 DVEE 12 D5 (MSB) 11 D4 10 DGND1
25 AGND 26 AVEE 27 CLKN 28 CLKP IEE -5.2V A 29 DVEE 30 D0 (LSB)
HI1826
31 D1 DGND1 DGND2 32 D2 DGND2
D3
9
1
2
3
4
5
6
7
8
FIGURE 4. SUPPLY CURRENT MEASUREMENT CIRCUIT ANALOG INPUT BIAS CURRENT MEASUREMENT CIRCUIT
4-8

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